Data · Chip manufacturing, at Analog Devices
Catching faulty chips and cutting test time
Two systems inside a chip factory. One stopped faulty chips that had passed every standard test. The other cut the time the tester spent tuning each chip.
- 1 · Outlier detectionNear-zero defective parts per million (DPPM) in production validation
- 2 · Wafer trim optimiserAbout $500,000 in production costs saved
How I approached both
Both projects followed the same path. I started from a cost, found its cause in past production test data, built a fix, and put it into the factory’s test flow with the design, production and IT teams.
1 · Outlier detection
Catching faulty chips that passed every test
A chip can pass every limit and still be unlike the rest.
- Normal chips
Inside the limits, and their readings move together - Flagged by the machine-learning check
Every reading is in range, but the combination is unusual - Caught by the standard test
At least one reading is outside its limit
- The cost
- Some faulty chips passed every standard test. They could have failed later, inside the customer’s product.
- What the data showed
- Those chips had every reading in range, but in an unusual combination. Checking one reading at a time could not see it.
- What I built
- A check that compared each chip’s readings as a set with the normal pattern, and flagged the ones that didn’t fit before they shipped.
- Result
- Near-zero defective parts per million (DPPM) in production validation
Technical detail
Each chip got one score for how far its combination of readings sat from the normal pattern (Mahalanobis distance), used alongside an XGBoost model. Chips that scored too far out were flagged even though they had passed. Built for a specific chip family, and served through production APIs built with Flask and Docker.
2 · Wafer trim optimiser
Cutting the time spent tuning each chip
A trim code sets each chip’s output voltage. Finding it faster cuts test time.
- Trim code
A setting stored on the chip that adjusts its output - Required output voltage
What the customer’s design needs. Each chip is trimmed until its output matches - Before: searching
The tester tries a code, measures the chip, and tries again - After: predicting
A machine-learning model predicts the code, and the tester starts its search from there
- The cost
- Every chip is tuned on the tester after manufacture. That tuning time was part of the cost of every chip.
- What the data showed
- Most of the tuning time went into searching for the right setting, with a measurement of the chip after each try.
- What I built
- A machine-learning model that predicted each chip’s setting, tuned with a genetic algorithm. The tester started its search from the prediction, so it searched less.
- Result
- Shorter test time, and about $500,000 in production costs saved
Technical detail
Trim codes are the tuning settings stored on each chip. A machine-learning model predicted each chip’s trim code from its test measurements. The model was tuned with a genetic algorithm, a search method that keeps and combines the best candidates over many rounds. It ran at wafer test, the stage where every chip is tested and tuned while still on the wafer, on Teradyne UltraFLEX testers. During the test, the test program requested the predicted setting through an API and started its search from there. Built for a specific chip family, and validated with the IC design and production engineering teams.
Built with
- Python
- XGBoost
- scikit-learn
- Flask
- Docker
What this means for a small team
The same idea applies to routine business data. An automated check flags the unusual numbers in a weekly report before it goes out, so a person only looks at what needs attention.
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